In today's rapidly advancing semiconductor manufacturing industry, there is a constant drive to reduce chip size and increase chip functionality. Stated alternatively, there is a drive to increase integration levels and reduce feature sizes of the devices that combine to form an integrated circuit chip. Using conventional processing techniques, contacts are formed by forming an opening through an insulating layer or layers, and exposing and contacting the top surface of a polysilicon or other interconnect lead which may be connected, for example, to a source/drain region formed in the substrate. Self-aligned contacts (SACs) now afford an increased level of integration by providing contact directly through an insulating layer or layers such as interlevel dielectric layers to directly contact the substrate region such as the source/drain region. In each case the contact openings are subsequently filled with a conductive or a semiconductor material.
As design rules allow for tighter and tighter geometries, and more closely spaced device components, it is a challenge to produce SACs that provide contact to source/drain regions while in close proximity to the associated gate structure. A gate structure typically includes a gate dielectric, a gate electrode, and other materials which form a stack aligned over a transistor channel that extends laterally from the source/drain regions formed on opposed sides of the gate structure. Gate structures commonly use dielectric spacers formed alongside the sidewalls of the gate structures. The sidewall spacers are typically formed of an oxide material, and it is common to form a nitride (silicon nitride, Si3N4) film over the gate structure including over the sidewall spacers. This is done because, when an etching operation is used to form an opening for an SAC that extends through interlevel dielectrics and exposes a source/drain region in close proximity to the gate structure, the nitride film prevents the sidewall spacer from being attacked because the nitride film is formed of a different material and is resistant to the etch chemistries and conditions used to etch the interlevel dielectrics and that may otherwise attack the oxide spaces. If the sidewall spacer is attacked and removed in part, and the sidewall of the gate electrode exposed, then the source/drain region and the gate structure itself will become shorted once the opening is filled with a conductive material, rendering the transistor inoperable. The nitride film is used to prevent such shorting from occurring. The etch selectivity between the interlevel dielectric desired to be etched and the nitride film which is desired to inhibit etching, is generally good. Therefore typical self-aligned contact processes exploit the etch selectivity between the interlevel dielectric and the nitride or other liner materials.
SAC processes using these conventional materials are becoming less manufacturable, however, as design rules allow for tighter geometries where high density plasma (HDP) dielectrics are required for use as pre-metal dielectrics. While HDP dielectrics are able to fill more aggressive aspect ratio gaps, their etch selectivity with respect to silicon nitride liner materials is generally poor. Moreover, aggressive design rules now provide for such SAC openings to be formed in closer proximity to the gate structure, and contacting the source/drain region. Therefore, the process is very alignment-sensitive, and a slight misalignment of the SAC opening may result in a contact opening exposing the nitride liner that extends along the oxide spacer adjacent the sidewall of the gate structure. This renders the gate structure more susceptible to attack during the etch process used to etch SAC openings in the HDP dielectric. Furthermore, conventional spacers extend to and terminate at the top surface of the gate structure. The nitride liner is most susceptible to erosion at the elbow point on top of the spacer due to general etch physics and the fact that the nitride liner may be thinnest at the point directly above the top of the spacer. If the nitride layer is eroded at this point, the underlying spacer which tapers to a point at this elbow point, may be attacked and a part of the gate electrode of the gate structure may be exposed. If so, the source/drain region will be shorted to the gate electrode when the contact structure is filled with a conductor.
One approach to addressing this problem is to improve the etch selectivity between the new HDP interlevel dielectrics and the nitride layer by using interlevel dielectric layers with increased dopant levels and/or using lower density fill materials such as ozone reacted oxides. The shortcoming of this approach, however, is that the higher dopant concentration materials have difficulty filling high aspect ratio structures. There is indeed a tradeoff between a high etch selectivity which inhibits attack of the nitride layer and therefore prevents shorting, and a dielectric material that is capable of filling high aspect ratio openings. Another shortcoming associated with highly doped dielectric layers such as boron or phosphorus doped silicon oxides is the associated thermal budget constraints as many advanced devices must be maintained at temperatures below 600 or 700° C.
There is thus a demonstrated need to produce a method and structure that enables self-aligned contact to source/drain regions that are in close proximity to the gate structure and which is resistant to shorting between the gate structure and the source/drain region being contacted.